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| HY29LV160 16 Mbit (2M x 8/1M x 16) Low Voltage Flash Memory KEY FEATURES n Single Power Supply Operation - Read, program and erase operations from 2.7 to 3.6 volts - Ideal for battery-powered applications High Performance - 70, 80, 90 and 120 ns access time versions Ultra-low Power Consumption (Typical Values At 5 Mhz) - Automatic sleep mode current: 1 A - Standby mode current: 1 A - Read current: 9 mA - Program/erase current: 20 mA Flexible Sector Architecture: - One 16 KB, two 8 KB, one 32 KB and thirty-one 64 KB sectors in byte mode - One 8 KW, two 4 KW, one 16 KW and thirty-one 32 KW sectors in word mode - Top or bottom boot block configurations available Sector Protection - Allows locking of a sector or sectors to prevent program or erase operations within that sector - Sectors lockable in-system or via programming equipment - Temporary Sector Unprotect allows changes in locked sectors (requires high voltage on RESET# pin) Fast Program and Erase Times - Sector erase time: 0.25 sec typical for each sector - Chip erase time: 8 sec typical - Byte program time: 9 s typical Unlock Bypass Program Command - Reduces programming time when issuing multiple program command sequences Automatic Erase Algorithm Preprograms and Erases Any Combination of Sectors or the Entire Chip Erase Suspend/Erase Resume - Suspends an erase operation to allow reading data from, or programming data to, a sector that is not being erased - Erase Resume can then be invoked to complete suspended erasure Automatic Program Algorithm Writes and Verifies Data at Specified Addresses n 100,000 Write Cycles per Sector Minimum n Data# Polling and Toggle Bits - Provide software confirmation of completion of program and erase operations Ready/Busy# Pin - Provides hardware confirmation of completion of program and erase operations Hardware Reset Pin (RESET#) Resets the Device to Reading Array Data Compliant With Common Flash Memory Interface (CFI) Specification - Flash device parameters stored directly on the device - Allows software driver to identify and use a variety of different current and future Flash products Compatible With JEDEC standards - Pinout and software compatible with single-power supply Flash devices - Superior inadvertent write protection Space Efficient Packaging - 48-pin TSOP and 48-ball FBGA packages n n n n n n n n n n LOGIC DIAGRAM 20 A[19:0] DQ[7:0] 7 CE# OE# WE# RESET# BYTE# DQ[14:8] DQ15/A-1 RY/BY# 8 n n n n Preliminary Revision 1.2, May 2001 HY29LV160 GENERAL DESCRIPTION The HY29LV160 is a 16 Mbit, 3 volt-only, CMOS Flash memory organized as 2,097,152 (2M) bytes or 1,048,576 (1M) words that is available in 48pin TSOP and 48-ball FBGA packages. Wordwide data (x16) appears on DQ[15:0] and bytewide (x8) data appears on DQ[7:0]. The HY29LV160 can be programmed and erased in-system with a single 3 volt VCC supply. Internally generated and regulated voltages are provided for program and erase operations, so that the device does not require a higher voltage VPP power supply to perform those functions. The device can also be programmed in standard EPROM programmers. Access times as low as 80 ns over the full operating voltage range of 2.7 - 3.6 volts, and 70 ns with a limited voltage range of 3.0 - 3.6 volts, are offered for timing compatibility with the zero wait state requirements of high speed microprocessors. To eliminate bus contention, the HY29LV160 has separate chip enable (CE#), write enable (WE#) and output enable (OE#) controls. The device is compatible with the JEDEC singlepower-supply Flash memory command set standard. Commands are written to the command register using standard microprocessor write timings. They are then routed to an internal state-machine that controls the erase and programming circuits. Device programming is performed a byte/word at a time by executing the four-cycle Program Command write sequence. This initiates an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Faster programming times can be achieved by placing the HY29LV160 in the Unlock Bypass mode, which requires only two write cycles to program data instead of four. The HY29LV160's sector erase architecture allows any number of array sectors to be erased and reprogrammed without affecting the data contents of other sectors. Device erasure is initiated by executing the Erase Command sequence. This initiates an internal algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. As during programming cycles, the device automatically times the erase pulse widths and verifies proper cell margin. Hardware Sector Protection optionally disables both program and erase operations in any combination of the sectors of 2 the memory array, while Temporary Sector Unprotect allows in-system erasure and code changes in previously protected sectors. Erase Suspend enables the user to put erase on hold for any period of time to read data from, or program data to, any sector that is not selected for erasure. True background erase can thus be achieved. The device is fully erased when shipped from the factory. Addresses and data needed for the programming and erase operations are internally latched during write cycles, and the host system can detect completion of a program or erase operation by observing the RY/BY# pin, or by reading the DQ[7] (Data# Polling) or DQ[6] (Toggle) status bits. Hardware data protection measures include a low VCC detector that automatically inhibits write operations during power transitions. After a program or erase cycle has been completed, or after assertion of the RESET# pin (which terminates any operation in progress), the device is ready to read data or to accept another command. Reading data out of the device is similar to reading from other Flash or EPROM devices. Two power-saving features are embodied in the HY29LV160. When addresses have been stable for a specified amount of time, the device enters Automatic Sleep mode. The host can also place the device into Standby mode. Power consumption is greatly reduced in both of these modes. Common Flash Memory Interface (CFI) To make Flash memories interchangeable and to encourage adoption of new Flash technologies, major Flash memory suppliers developed a flexible method of identifying Flash memory sizes and configurations in which all necessary Flash device parameters are stored directly on the device. Parameters stored include memory size, byte/word configuration, sector configuration, necessary voltages and timing information. This allows one set of software drivers to identify and use a variety of different current and future Flash products. The standard which details the software interface necessary to access the device to identify it and to determine its characteristics is the Common Flash Memory Interface (CFI) Specification. The HY29LV160 is fully compliant with this specification. Rev. 1.2/May 01 HY29LV160 BLOCK DIAGRAM DQ[15:0] A[19:0], A-1 STATE CONTROL DQ[15:0] WE# CE# OE# BYTE# RESET# RY/BY# PROGRAM VOLTAGE GENERATOR COMMAND REGISTER ERASE VOLTAGE GENERATOR AND SECTOR SWITCHES I/O CONTROL I/O BUFFERS DATA LATCH V C C DETECTOR TIMER A[19:0], A-1 ADDRESS LATCH Y-DECODER Y-GATING X-DECODER 16 Mb FLASH MEMORY ARRAY SIGNAL DESCRIPTIONS Name A[19:0] DQ[15]/A[-1], DQ[14:0] BY TE# CE# Type Inputs Description Address, active High. These 20 inputs, combined with the DQ[15]/A[-1] input in Byte mode, select one location within the array for read or write operations. Data Bus, active High. These pins provide an 8- or 16-bit data path for read Inputs/Outputs and write operations. In Byte mode, DQ[15]/A[-1] is used as the LSB of the 21-bit Tri-state byte address input. DQ[14:8] are unused and remain tri-stated in Byte mode. Input Input Byte Mode, active Low. Low selects Byte mode, High selects Word mode. Chip Enable, active Low. This input must be asserted to read data from or write data to the HY 29LV160. When High, the data bus is tri-stated and the device is placed in the Standby mode. Output Enable, active Low. Asserted for read operations and negated for write operations. BY TE# determines whether a byte or a word is read during the read operation. Write Enable, active Low. Controls writing of commands or command sequences in order to program data or erase sectors of the memory array. A write operation takes place when WE# is asserted while CE# is Low and OE# is High. Hardware Reset, active Low. Provides a hardware method of resetting the HY 29LV160 to the read array state. When the device is reset, it immediately terminates any operation in progress. While RESET# is asserted, the device will be in the Standby mode. Re a dy / Bus y St a t us . I nd ic a t e s w he t he r a w r it e o r e r a s e c o mma nd is in progress or has been completed. Remains Low w hile the device is actively programming data or erasing, and goes High when it is ready to read array data. 3-volt (nominal) power supply. Power and signal ground. OE# Input WE# Input RESET# Input RY /BY # VCC VSS Output Open Drain --- Rev. 1.2/May 01 3 HY29LV160 PIN CONFIGURATIONS 48-Ball FBGA (Top View, Balls Facing Down) A6 A[13] B6 A[12] C6 A[14] D6 A[15] E6 A[16] F6 BYTE# G6 DQ[15]/A[-1] H6 V SS A5 A[9] B5 A[8] C5 A[10] D5 A[11] E5 DQ[7] F5 DQ[14] G5 DQ[13] H5 DQ[6] A4 WE# B4 RESET# C4 NC D4 A[19] E4 DQ[5] F4 DQ[12] G4 V CC H4 DQ[4] A3 RY/BY# B3 NC C3 A[18] D3 NC E3 DQ[2] F3 DQ[10] G3 DQ[11] H3 DQ[3] A2 A[7] B2 A[17] C2 A[6] D2 A[5] E2 DQ[0] F2 DQ[8] G2 DQ[9] H2 DQ[1] A1 A[3] B1 A[4] C1 A[2] D1 A[1] E1 A[0] F1 CE# G1 OE# H1 V SS A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[19] NC WE# RESET# NC NC RY/BY# A[18] A[17] A[7] A[6] A[5] A[4] A[3] A[2] A[1] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 TSOP48 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A[16] BYTE# V SS DQ[15]/A[-1] DQ[7] DQ[14] DQ[6] DQ[13] DQ[5] DQ[12] DQ[4] V CC DQ[11] DQ[3] DQ[10] DQ[2] DQ[9] DQ[1] DQ[8] DQ[0] OE# V SS CE# A[0] 4 Rev. 1.2/May 01 HY29LV160 CONVENTIONS Unless otherwise noted, a positive logic (active High) convention is assumed throughout this document, whereby the presence at a pin of a higher, more positive voltage (VIH) causes assertion of the signal. A `#' symbol following the signal name, e.g., RESET#, indicates that the signal is asserted in the Low state (VIL). See DC specifications for VIH and VIL values. MEMORY ARRAY ORGANIZATION The 16 Mbit Flash memory array is organized into 35 blocks called sectors (S0, S1, . . . , S34). A sector is the smallest unit that can be erased and that can be protected to prevent accidental or unauthorized erasure. See the `Bus Operations' and `Command Definitions' sections of this document for additional information on these functions. In the HY29LV160, four of the sectors, which comprise the boot block, vary in size from 8 to 32 BUS OPERATIONS Device bus operations are initiated through the internal command register, which consists of sets of latches that store the commands, along with the address and data information, if any, needed to execute the specific command. The command register itself does not occupy any addressable memory location. The contents of the command register serve as inputs to an internal state machine whose outputs control the operation of the device. Table 3 lists the normal bus operations, the inputs and control levels they require, and the resulting outputs. Certain bus operations require a high voltage on one or more device pins. Those are described in Table 4. Read Operation Whenever a signal is separated into numbered bits, e.g., DQ[7], DQ[6], ..., DQ[0], the family of bits may also be shown collectively, e.g., as DQ[7:0]. The designation 0xNNNN (N = 0, 1, 2, . . . , 9, A, . . . , E, F) indicates a number expressed in hexadecimal notation. The designation 0bXXXX indicates a number expressed in binary notation (X = 0, 1). Kbytes (4 to 16 Kwords), while the remaining 31 sectors are uniformly sized at 64 Kbytes (32 Kwords). The boot block can be located at the bottom of the address range (HY29LV160B) or at the top of the address range (HY29LV160T). Tables 1 and 2 define the sector addresses and corresponding address ranges for the top and bottom boot block versions of the HY29LV160. ware reset to ensure that no spurious alteration of the memory content occurs during the power transition. No command is necessary in this mode to obtain array data, and the device remains enabled for read accesses until the command register contents are altered. This device features an Erase Suspend mode. While in this mode, the host may read the array data from any sector of memory that is not marked for erasure. If the host reads from an address within an erase-suspended (or erasing) sector, or while the device is performing a byte or word program operation, the device outputs status data instead of array data. After completing an Automatic Program or Automatic Erase algorithm within a sector, that sector automatically returns to the read array data mode. After completing a programming operation in the Erase Suspend mode, the system may once again read array data with the same exception noted above. The host must issue a hardware reset or the software reset command to return a sector to the read array data mode if DQ[5] goes high during a program or erase cycle, or to return the device to the read array data mode while it is in the Electronic ID mode. Data is read from the HY29LV160 by using standard microprocessor read cycles while placing the byte or word address on the device's address inputs. The host system must drive the CE# and OE# pins LOW and drive WE# high for a valid read operation to take place. The BYTE# pin determines whether the device outputs array data in words (DQ[15:0]) or in bytes (DQ[7:0]). The HY29LV160 is automatically set for reading array data after device power-up and after a hard- Rev. 1.2/May 01 5 HY29LV160 Table 1. HY29LV160T (Top Boot Block) Memory Array Organization Sector Address 1 SectSize or (KB/KW) A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 32/16 8/4 8/4 16/8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X Byte Mode Address Range 2 0x000000 - 0x00FFFF 0x010000 - 0x01FFFF 0x020000 - 0x02FFFF 0x030000 - 0x03FFFF 0x040000 - 0x04FFFF 0x050000 - 0x05FFFF 0x060000 - 0x06FFFF 0x070000 - 0x07FFFF 0x080000 - 0x08FFFF 0x090000 - 0x09FFFF 0x0A0000 - 0x0AFFFF 0x0B0000 - 0x0BFFFF 0x0C0000 - 0x0CFFFF 0x0D0000 - 0x0DFFFF 0x0E0000 - 0x0EFFFF 0x0F0000 - 0x0FFFFF 0x100000 - 0x10FFFF 0x110000 - 0x11FFFF 0x120000 - 0x12FFFF 0x130000 - 0x13FFFF 0x140000 - 0x14FFFF 0x150000 - 0x15FFFF 0x160000 - 0x16FFFF 0x170000 - 0x17FFFF 0x180000 - 0x18FFFF 0x190000 - 0x19FFFF 0x1A0000 - 0x1AFFFF 0x1B0000 - 0x1BFFFF 0x1C0000 - 0x1CFFFF 0x1D0000 - 0x1DFFFF 0x1E0000 - 0x1EFFFF 0x1F0000 - 0x1F7FFF 0x1F8000 -0x1F9FFF 0x1FA000 - 0x1FBFFF 0x1FC000 - 0x1FFFFF Word Mode Address Range 3 0x00000 - 0x07FFF 0x08000 - 0x0FFFF 0x10000 - 0x17FFF 0x18000 - 0x1FFFF 0x20000 - 0x27FFF 0x28000 - 0x2FFFF 0x30000 - 0x37FFF 0x38000 - 0x3FFFF 0x40000 - 0x47FFF 0x48000 - 0x4FFFF 0x50000 - 0x57FFF 0x58000 - 0x5FFFF 0x60000 - 0x67FFF 0x68000 - 0x6FFFF 0x70000 - 0x77FFF 0x78000 - 0x7FFFF 0x80000 - 0x87FFF 0x88000 - 0x8FFFF 0x90000 - 0x97FFF 0x98000 - 0x9FFFF 0xA0000 - 0xA7FFF 0xA8000 - 0xAFFFF 0xB0000 - 0xB7FFF 0xB8000 - 0xBFFFF 0xC0000 - 0xC7FFF 0xC8000 - 0xCFFFF 0xD0000 - 0xD7FFF 0xD8000 - 0xDFFFF 0xE0000 - 0xE7FFF 0xE8000 - 0xEFFFF 0xF0000 - 0xF7FFF 0xF8000 - 0xFBFFF 0xFC000 - 0xFCFFF 0XFD000 - 0xFDFFF 0xFE000 - 0xFFFFF Notes: 1. `X' indicates don't care. 2. `0xN. . . N' indicates an address in hexadecimal notation. 3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0]. 6 Rev. 1.2/May 01 HY29LV160 Table 2. HY29LV160B (Bottom Boot Block) Memory Array Organization Sector Address 1 Sect- Size or (KB/KW) A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] S0 S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 S17 S18 S19 S20 S21 S22 S23 S24 S25 S26 S27 S28 S29 S30 S31 S32 S33 S34 16/8 8/4 8/4 32/16 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 64/32 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X 0 1 X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Byte Mode Address Range 2 0x000000 - 0x003FFF 0x004000 - 0x005FFF 0x006000 - 0x007FFF 0x008000 - 0x00FFFF 0x010000 - 0x01FFFF 0x020000 - 0x02FFFF 0x030000 - 0x03FFFF 0x040000 - 0x04FFFF 0x050000 - 0x05FFFF 0x060000 - 0x06FFFF 0x070000 - 0x07FFFF 0x080000 - 0x08FFFF 0x090000 - 0x09FFFF 0x0A0000 - 0x0AFFFF 0x0B0000 - 0x0BFFFF 0x0C0000 - 0x0CFFFF 0x0D0000 - 0x0DFFFF 0x0E0000 - 0x0EFFFF 0x0F0000 - 0x0FFFFF 0x100000 - 0x10FFFF 0x110000 - 0x11FFFF 0x120000 - 0x12FFFF 0x130000 - 0x13FFFF 0x140000 - 0x14FFFF 0x150000 - 0x15FFFF 0x160000 - 0x16FFFF 0x170000 - 0x17FFFF 0x180000 - 0x18FFFF 0x190000 - 0x19FFFF 0x1A0000 - 0x1AFFFF 0x1B0000 - 0x1BFFFF 0x1C0000 - 0x1CFFFF 0x1D0000 - 0x1DFFFF 0x1E0000 - 0x1EFFFF 0x1F0000 - 0x1FFFFF Word Mode Address Range 3 0x00000 - 0x01FFF 0x02000 - 0x02FFF 0X03000 - 0x03FFF 0x04000 - 0x07FFF 0x08000 - 0x0FFFF 0x10000 - 0x17FFF 0x18000 - 0x1FFFF 0x20000 - 0x27FFF 0x28000 - 0x2FFFF 0x30000 - 0x37FFF 0x38000 - 0x3FFFF 0x40000 - 0x47FFF 0x48000 - 0x4FFFF 0x50000 - 0x57FFF 0x58000 - 0x5FFFF 0x60000 - 0x67FFF 0x68000 - 0x6FFFF 0x70000 - 0x77FFF 0x78000 - 0x7FFFF 0x80000 - 0x87FFF 0x88000 - 0x8FFFF 0x90000 - 0x97FFF 0x98000 - 0x9FFFF 0xA0000 - 0xA7FFF 0xA8000 - 0xAFFFF 0xB0000 - 0xB7FFF 0xB8000 - 0xBFFFF 0xC0000 - 0xC7FFF 0xC8000 - 0xCFFFF 0xD0000 - 0xD7FFF 0xD8000 - 0xDFFFF 0xE0000 - 0xE7FFF 0xE8000 - 0xEFFFF 0xF0000 - 0xF7FFF 0xF8000 - 0xFFFFF Notes: 1. `X' indicates don't care. 2. `0xN. . . N' indicates an address in hexadecimal notation. 3. The address range in byte mode is A[19:0, -1]. The address range in word mode is A[19:0]. Rev. 1.2/May 01 7 HY29LV160 Table 3. HY29LV160 Normal Bus Operations 1 Operation Read Write Output Disable CE# Normal Standby CE# Deep Standby Hardware Reset (Normal Standby) Hardware Reset (Deep Standby) CE# L L L H VCC 0.3V X X OE# L H H X X X X WE# H L H X X X X RESET # H H H H VCC 0.3V L VSS 0.3V Address 2 AIN AIN X X X X X DQ[7:0] DOUT DIN High-Z High-Z High-Z High-Z High-Z DQ[15:8] 3 BYTE# = H BYTE# = L DOUT DIN High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z High-Z Notes: 1. L = VIL, H = VIH, X = Don't Care (L or H), DOUT = Data Out, DIN = Data In. See DC Characteristics for voltage levels. 2. Address is A[19:0, -1] in Byte Mode and A[19:0] in Word Mode. 3. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L). Table 4. HY29LV160 Bus Operations Requiring High Voltage 1, 2 DQ[15:8] Operation 3 Sector Protect Sector Unprotect Temporary Sector Unprotect 6 Manufacturer Code Device HY29LV160B Code HY29LV160T Sector Protection Verification CE# OE# WE# RESET # A[19:12] A[9] A[6] A[1] A[0] L L -L L H H -L L L L -H H VID VID VID H H SA 4 X -X X X X -VID VID L H -L L H H -L L L L -L H DQ[7:0] DIN DIN -0xAD 0x49 0xC4 0x00 = Unprotected 0x01 = Protected BYT E# BYT E# =H = L5 X X -X 0x22 X X -High-Z High-Z L L H H SA 4 VID L H L X High-Z Notes: 1. L = VIL, H = VIH, X = Don't Care (L OR H). See DC Characteristics for voltage levels. 2. Address bits not specified are Don't Care. 3. See text and Appendix A for additional information. 4. SA = Sector Address. See Tables 1 and 2. 5. DQ[15] is the A[-1] input in Byte Mode (BYTE# = L). 6. Normal read, write and output disable operations are used in this mode. See Table 3. 8 Rev. 1.2/May 01 HY29LV160 Write Operation Certain operations, including programming data and erasing sectors of memory, require the host to write a command or command sequence to the HY29LV160. Writes to the device are performed by placing the byte or word address on the device's address inputs while the data to be written is input on DQ[15:0] (BYTE# = High) or DQ[7:0] (BYTE# = Low). The host system must drive the CE# and WE# pins Low and drive OE# High for a valid write operation to take place. All addresses are latched on the falling edge of WE# or CE#, whichever happens later. All data is latched on the rising edge of WE# or CE#, whichever happens first. The "Device Commands" section of this data sheet provides details on the specific device commands implemented in the HY29LV160. Standby Operation When the system is not reading or writing to the device, it can place the HY29LV160 in the Standby mode. In this mode, current consumption is greatly reduced, and the data bus outputs are placed in the high impedance state, independent of the OE# input. The Standby mode can be invoked using two methods. The device enters the CE# Deep Standby mode when the CE# and RESET# pins are both held at VCC 0.3V. Note that this is a more restricted voltage range than VIH . If both CE# and RESET# are held at VIH, but not within VCC 0.3V, the device will be in the CE# Normal Standby mode, but the standby current will be greater. The device enters the RESET# Deep Standby mode when the RESET# pin is held at VSS 0.3V. If RESET# is held at VIL but not within VSS 0.3V, the device will be in the RESET# Normal Standby mode, but the standby current will be greater. See Reset Operation for additional information. The device requires standard access time (tCE) for read access when the device is in either of the standby modes, before it is ready to read data. If the device is deselected during erasure or programming, it continues to draw active current until the operation is completed. Sleep Mode The sleep mode automatically minimizes device power consumption. This mode is automatically Rev. 1.2/May 01 entered when addresses remain stable for tACC + 30 ns (typical) and is independent of the state of the CE#, WE#, and OE# control signals. Standard address access timings provide new data when addresses are changed. While in sleep mode, output data is latched and always available to the system. NOTE: Sleep mode is entered only when the device is in read mode. It is not entered if the device is executing an automatic algorithm, if it is in erase suspend mode, or during receipt of a command sequence. Output Disable Operation When the OE# input is at VIH, output data from the device is disabled and the data bus pins are placed in the high impedance state. Reset Operation The RESET# pin provides a hardware method of resetting the device to reading array data. When the RESET# pin is driven low for the minimum specified period, the device immediately terminates any operation in progress, tri-states the data bus pins, and ignores all read/write commands for the duration of the RESET# pulse. The device also resets the internal state machine to reading array data. If an operation was interrupted by the assertion of RESET#, it should be reinitiated once the device is ready to accept another command sequence to ensure data integrity. Current is reduced for the duration of the RESET# pulse as described in the Standby Operation section above. If RESET# is asserted during a program or erase operation, the RY/BY# pin remains Low (busy) until the internal reset operation is complete, which requires a time of tREADY (during Automatic Algorithms). The system can thus monitor RY/BY# to determine when the reset operation completes, and can perform a read or write operation tRB after RY/BY# goes High. If RESET# is asserted when a program or erase operation is not executing (RY/ BY# pin is High), the reset operation is completed within a time of tRP. In this case, the host can perform a read or write operation tRH after the RESET# pin returns High . The RESET# pin may be tied to the system reset signal. Thus, a system reset would also reset the device, enabling the system to read the boot-up firmware from the Flash memory. 9 HY29LV160 Sector Protect Operation The hardware sector protection feature disables both program and erase operations in any sector or combination of sectors. This function can be implemented either in-system or by using programming equipment. The method intended for programming equipment requires a high voltage (VID) on address pin A[9] and the control pins. Refer to the Appendix at the end of this document for additional information. The in-system method requires VID only on the RESET# pin and uses standard microprocessor bus cycle timing to implement sector protection. The flow chart in Figure 1 illustrates the algorithm. The HY29LV160 is shipped with all sectors unprotected. It is possible to determine whether a sector is protected or unprotected. See the Electronic ID Mode section for details. Sector Unprotect Operation The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. This function can be implemented either in-system or by using programming equipment. Note that to unprotect any sector, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. Also, the unprotect procedure will cause all sectors to become unprotected, thus, sectors that require protection must be protected again after the unprotect procedure is run. The method intended for programming equipment requires a high voltage (VID) on address pin A[9] and the control pins. Refer to the Appendix for additional information. The in-system method requires VID only on the RESET# pin and uses standard microprocessor bus cycle timing to implement sector unprotection. The flow chart in Figure 2 illustrates the algorithm. Temporary Sector Unprotect Operation This feature allows temporary unprotection of previously protected sectors to allow changing the data in-system. Sector Unprotect mode is activated by setting the RESET# pin to VID. While in this mode, formerly protected sectors can be programmed or erased by invoking the appropriate commands (see Device Commands section). Once VID is removed from RESET#, all the previously protected sectors are protected again. Figure 3 illustrates the algorithm. START Wait 150 us R E S E T # = V IH R E S E T # = V ID Write 0x40 to Address Write Reset Command Wait 1 us Read from Address SECTOR PROTECT COMPLETE Data = 0x01? TRYCNT = 1 YES Set Address: A[19:12] = Sector to Protect A[6] = 0, A[1] = 1, A[0] = 0 Protect Another Sector? Write 0x60 to Address YES NO NO Increment TRYCNT DEVICE FAILURE NO TRYCNT = 25? YES Write 0x60 to device Figure 1. Sector Protect Algorithm 10 Rev. 1.2/May 01 HY29LV160 START (Note: All sectors must be protected prior to unprotecting any sector) Set Address: A[19:12] = Sector SNUM A[6] = 1, A]1] = 1, A]0] = 0 R E S E T # = V IH TRYCNT = 1 SNUM = 0 Write Reset Command Write 0x40 to Address SECTOR UNPROTECT COMPLETE R E S E T # = V ID Read from Address Wait 1 us Data = 0x00? Write 0x60 to device YES Set Address: A[6] = 1, A]1] = 1, A]0] = 0 SNUM = 34? Write 0x60 to Address Wait 15 ms NO SNUM = SNUM + 1 YES NO Increment TRYCNT DEVICE FAILURE NO TRYCNT = 1000? YES Figure 2. Sector Unprotect Algorithm START grammed with its corresponding programming algorithm. Two methods are provided for accessing the Electronic ID data. The first requires VID on address pin A[9], with additional requirements for obtaining specific data items listed in Table 4. The Electronic ID data can also be obtained by the host through specific commands issued via the command register, as described in the `Device Commands' section of this data sheet. While in the high-voltage Electronic ID mode, the system may read at specific addresses to obtain certain device identification and status information: R E S E T # = V ID (All protected sectors become unprotected) Perform Program or Erase Operations R E S E T # = V IH (All previously protected sectors return to protected state) TEMPORARY SECTOR UNPROTECT COMPLETE A read cycle at address 0xXXX00 retrieves the manufacturer code. A read cycle at address 0xXXX01 in Word mode or 0xXXX02 in Byte mode returns the device code. A read cycle containing a sector address (SA) in A[19:12] and the address 0x02 in Word mode or 0x04 in Byte mode, returns 0x01 if that sector is protected, or 0x00 if it is unprotected. Figure 3. Temporary Sector Unprotect Algorithm Electronic ID Operation (High Voltage Method) The Electronic ID mode provides manufacturer and device identification and sector protection verification through codes output on DQ[15:0]. This mode is intended primarily for programming equipment to automatically match a device to be proRev. 1.2/May 01 11 HY29LV160 DEVICE COMMANDS Device operations are initiated by writing designated address and data command sequences into the device. Addresses are latched on the falling edge of WE# or CE#, whichever happens later. Data is latched on the rising edge of WE# or CE#, whichever happens first. A command sequence is composed of one, two or three of the following sub-segments: an unlock cycle, a command cycle and a data cycle. Table 5 summarizes the composition of the valid command sequences implemented in the HY29LV160, and these sequences are fully described in Table 6 and in the sections that follow. Writing incorrect address and data values or writing them in the improper sequence resets the HY29LV160 to the Read mode. Reading Data The device automatically enters the Read mode after device power-up, after the RESET# input is asserted and upon the completion of certain commands. Commands are not required to retrieve data in this mode. See Read Operation section for additional information. Reset Command Writing the Reset command resets the sectors to the Read or Erase-Suspend mode. Address bits are don't cares for this command. As described above, a Reset command is not normally required to begin reading array data. However, a Reset command must be issued in order to read array data in the following cases: * If the device is in the Electronic ID mode, a Reset command must be written to return to the Read mode. If the device was in the Erase Suspend mode when the device entered the Electronic ID mode, writing the Reset command returns the device to the Erase Suspend mode. Note: When in the Electronic ID bus operation mode, the device returns to the Read mode when VID is removed from the A[9] pin. The Reset command is not required in this case. Table 5. Composition of Command Sequences Command Sequence Reset Read Byte/Word Program Unlock Bypass Unlock Bypass Reset Unlock Bypass Byte/Word Program Chip Erase Sector Erase Erase Suspend Erase Resume Electronic ID CFI Query Number of Bus Cycles Unlock Command 0 0 2 2 0 0 4 4 0 0 2 0 1 0 1 1 1 1 1 1 1 1 1 1 Data 0 Note 1 1 0 1 1 1 1 (Note 2) 0 0 Note 3 Note 4 Notes: 1. Any number of Flash array read cycles are permitted. 2. Additional data cycles may follow. See text. 3. Any number of Electronic ID read cycles are permitted. 4. Any number of CFI data read cycles are permitted. * If DQ[5] (Exceeded Time Limit) goes High during a program or erase operation, a Reset command must be invoked to return the sectors to the Read mode (or to the Erase Suspend mode if the device was in Erase Suspend when the Program command was issued). The Reset command may also be used to abort certain command sequences: * In a Sector Erase or Chip Erase command sequence, the Reset command may be written at any time before erasing actually begins, including, for the Sector Erase command, between the cycles that specify the sectors to be erased (see Sector Erase command description). This aborts the command and resets the device to the Read mode. Once erasure begins, however, the device ignores the Reset command until the operation is complete. In a Program command sequence, the Reset command may be written between the sequence cycles before programming actually begins. This aborts the command and resets the device to the Read mode, or to the Erase Suspend mode if the Program command sequence Rev. 1.2/May 01 * * If the device is in the CFI Query mode, a Reset command must be written to return to the array Read mode. 12 Table 6. HY29LV160 Command Sequences Bus Cycles 1, 2, 3 Write Cycles Add RA XXX 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA XXX XXX 555 AAA 555 AAA 555 AAA 055 0AA AA 555 2AA AA 555 55 55 2AA AA 555 55 2AA 555 AAA 555 AAA 555 AAA 30 90 90 90 X00 X01 X02 AD 22C4 (Top Boot), 2249 (Bottom Boot) C4 (Top Boot), 49 (Bottom Boot) (SA)X02 00 = Unprotected Sector (SA)X04 01 = Protected Sector B0 AA 555 AAA 55 80 2AA 555 AA 555 AAA 55 80 AAA 555 AAA 2AA 555 555 A0 PA PD AA AA 2AA 555 2AA 555 55 55 555 AAA SA 10 30 90 XXX 00 AA 555 AAA 55 2AA 555 AA 555 AAA 55 A0 PA PD 2AA 555 F0 RD Electronic ID 6 Rev. 1.2/May 01 Command Sequence Data Add Data Add Data Add Data Add Data Add 0 1 Word Byte Word Byte 2 Word Byte Word Byte Word Byte 1 1 Word Byte Word Byte Word Byte Word Byte 3 3 3 6 6 2 3 4 First Second T hird Fourth Fifth Sixth Data Read Reset 7 Normal Program Unlock Bypass 20 Unlock Bypass Reset Unlock Bypass Program 9 Chip Erase Sector Erase Erase Suspend 4 Erase Resume 5 Manufacturer Code Device Code Sector Protect Verify Common Flash Interface (CFI) Query 8 1 98 Legend: X = Don't Care RA = Memory address of data to be read RD = Data read from location RA during the read operation PA = Address of the data to be programmed PD = Data to be programmed at address PA SA = Sector address of sector to be erased or verified (see Note 3 and Tables 1 and 2). HY29LV160 Notes: See next page for notes. 13 HY29LV160 Notes for Table 6: 1. All values are in hexadecimal. DQ[15:8] are don't care for unlock and command cycles. 2. All bus cycles are write operations unless otherwise noted. 3. Address is A[10:0] in Word mode and A[10:0, -1] in Byte mode. A[19:11] are don't care except as follows: * For RA and PA, A[19:11] are the upper address bits of the byte to be read or programmed. * For the sixth cycle of Sector Erase, SA = A[19:12] are the sector address of the sector to be erased. * For the fourth cycle of Sector Protect Verify, SA = A[19:12] are the sector address of the sector to be verified. 4. The Erase Suspend command is valid only during a sector erase operation. The system may read and program in nonerasing sectors, or enter the Electronic ID mode, while in the Erase Suspend mode. 5. The Erase Resume command is valid only during the Erase Suspend mode. 6. The fourth bus cycle is a read cycle. 7. The command is required only to return to the Read mode when the device is in the Electronic ID command mode or in the CFI Query mode. It must also be issued to return to read mode if DQ[5] goes High during a program or erase operation. It is not required for normal read operations. 8 This command is valid only when the device is in Read mode or in Electronic ID mode. 9. The Unlock Bypass command is required prior to the Unlock Bypass Program command. is written while the device is in the Erase Suspend mode. Once programming begins, however, the device ignores the Reset command until the operation is complete. * The Reset command may be written between the cycles in an Electronic ID command sequence to abort that command. As described above, once in the Electronic ID mode, the Reset command must be written to return to the array Read mode. should be reinitiated once the reset operation is complete. Programming is allowed in any sequence. Only erase operations can convert a stored "0" to a "1". Thus, a bit cannot be programmed from a "0" back to a "1". Attempting to do so may halt the operation and set DQ[5] to "1", or cause the Data# Polling algorithm to indicate the operation was successful. However, a succeeding read will show that the data is still "0". Figure 4 illustrates the programming procedure. Unlock Bypass/Bypass Program/Bypass Reset Commands Unlock bypass provides a faster method for the host system to program the device. As shown in Table 6, the Unlock Bypass command sequence consists of two unlock write cycles followed by a third write cycle containing the Unlock Bypass command, 0x20. In the Unlock Bypass mode, a two-cycle Unlock Bypass Program command sequence is used instead of the standard four-cycle Program sequence to invoke a programming operation. The first cycle in this sequence contains the Unlock Bypass Program command, 0xA0, and the second cycle specifies the program address and data, thus eliminating the initial two unlock cycles required in the standard Program command sequence Additional data is programmed in the same manner. During the Unlock Bypass mode, only the Unlock Bypass program and Unlock Bypass Reset commands are valid. To exit the Unlock Bypass mode, the host must issue the two-cycle Unlock Bypass Reset command sequence shown in Table 6. The device then returns to the array Read mode. Rev. 1.2/May 01 Program Command The system programs the device a word or byte at a time by issuing the appropriate four-cycle program command sequence as shown in Table 6. The sequence begins by writing two unlock cycles, followed by the program setup command and, lastly, the program address and data. This initiates the Automatic Program algorithm which automatically provides internally generated program pulses and verifies the programmed cell margin. The host is not required to provide further controls or timings during this operation. When the Automatic Program algorithm is complete, the device returns to the array Read mode (or to the Erase Suspend mode if the device was in Erase Suspend when the Program command was issued). Several methods are provided to allow the host to determine the status of the programming operation, as described in the Write Operation Status section. Commands written to the device during execution of the Automatic Program algorithm are ignored. Note that a hardware reset immediately terminates the programming operation. To ensure data integrity, the aborted Program command sequence 14 HY29LV160 START Check Programming Status (See Write Operation Status Section) Enable Fast Programming? DQ[5] Error Exit NO Programming Verified YES Issue UNLOCK BYPASS Command NO Last Word/Byte Done? YES Setup Next Address/Data for Program Operation NO Unlock Bypass Mode? NO Unlock Bypass Mode? YES Issue UNLOCK BYPASS RESET Command Issue NORMAL PROGRAM Command YES Issue UNLOCK BYPASS PROGRAM Command PROGRAMMING COMPLETE GO TO ERROR RECOVERY PROCEDURE Figure 4. Normal and Unlock Bypass Programming Procedures Chip Erase Command The Chip Erase command sequence consists of two unlock cycles, followed by a set-up command, two additional unlock cycles and then the Chip Erase command. This sequence invokes the Automatic Erase algorithm which automatically preprograms and verifies the entire memory for an all zero data pattern prior to electrical erase. The host system is not required to provide any controls or timings during these operations. Commands written to the device during execution of the Automatic Erase algorithm are ignored. Note that a hardware reset immediately terminates the chip erase operation. To ensure data integrity, the aborted Chip Erase command sequence should be reissued once the reset operation is complete. When the Automatic Erase algorithm is complete, the device returns to the array Read mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section. Figure 5 illustrates the chip erase procedure. Sector Erase Command The Sector Erase command sequence consists of two unlock cycles, followed by the Erase command, two additional unlock cycles and then the sector erase data cycle, which specifies the sector to be erased. As described later in this section, multiple sectors can be specified for erasure with a single command sequence. During sector erase, all specified sectors are erased sequentially. The data in sectors not specified for erasure, as well as the data in any protected sectors, 15 START Issue CHIP ERASE Command Sequence Check Erase Status (See Write Operation Status Section) Normal Exit DQ[5] Error Exit CHIP ERASE COMPLETE GO TO ERROR RECOVERY Figure 5. Chip Erase Procedure Rev. 1.2/May 01 HY29LV160 even if specified for erasure, is not affected by the sector erase operation. The Sector Erase command sequence starts the Automatic Erase algorithm, which preprograms and verifies the specified unprotected sectors for an all zero data pattern prior to electrical erase. The device then provides the required number of internally generated erase pulses and verifies cell erasure within the proper cell margins. The host system is not required to provide any controls or timings during these operations. After the sector erase data cycle (the sixth bus cycle) of the command sequence is issued, a sector erase time-out of 50 s, measured from the rising edge of the final WE# pulse in that bus cycle, begins. During this time-out window, an additional sector erase data cycle, specifying the sector address of another sector to be erased, may be written into an internal sector erase buffer. This buffer may be loaded in any sequence, and the number of sectors specified may be from one sector to all sectors. The only restriction is that the time between these additional data cycles must be less than 50 s, otherwise erasure may begin before the last data cycle is accepted. To ensure that all data cycles are accepted, it is recommended that host processor interrupts be disabled during the time that the additional cycles are being issued and then be re-enabled afterwards. If all sectors specified for erasing are protected, the device returns to reading array data after approximately 100 s. If at least one specified sector is not protected, the erase operation erases the unprotected sectors, and ignores the command for the sectors that are protected. The system can monitor DQ[3] to determine if the 50 s sector erase time-out has expired, as described in the Write Operation Status section. If the time between additional sector erase data cycles can be insured to be less than the timeout, the system need not monitor DQ[3]. Any command other than Sector Erase or Erase Suspend during the time-out period resets the device to reading array data. The system must then rewrite the command sequence, including any additional sector erase data cycles. Once the sector erase operation itself has begun, only the Erase Suspend command is valid. All other commands are ignored. As for the Chip Erase command, note that a hardware reset immediately terminates the sector erase operation. To ensure data integrity, the START Check Erase Status (See Write Operation Status Section) Normal Exit Write First Five Cycles of SECTOR ERASE Command Sequence ERASE COMPLETE Setup First (or Next) Sector Address for Erase Operation GO TO ERROR RECOVERY DQ[5] Error Exit Write Last Cycle (SA/0x30) of SECTOR ERASE Command Sequence NO Sector Erase Time-out (DQ[3]) Expired? Sectors which require erasure but which were not specified in this erase cycle must be erased later using a new command sequence Erase An Additional Sector? YES YES NO Figure 6. Sector Erase Procedure 16 Rev. 1.2/May 01 HY29LV160 aborted Sector Erase command sequence should be reissued once the reset operation is complete. When the Automatic Erase algorithm terminates, the device returns to the array Read mode. Several methods are provided to allow the host to determine the status of the erase operation, as described in the Write Operation Status section. Figure 6 illustrates the Sector Erase procedure. Erase Suspend/Erase Resume Commands The Erase Suspend command allows the system to interrupt a sector erase operation to read data from, or program data in, any sector not being erased. The command causes the erase operation to be suspended in all sectors specified for erasure. This command is valid only during the sector erase operation, including during the 50 s time-out period at the end of the command sequence, and is ignored if it is issued during chip erase or programming operations. The HY29LV160 requires a maximum of 20 s to suspend the erase operation if the Erase Suspend command is issued during sector erasure. However, if the command is written during the timeout, the time-out is terminated and the erase operation is suspended immediately. Once the erase operation has been suspended, the system can read array data from or program data to any sector not specified for erasure. Normal read and write timings and command definitions apply. Reading at any address within erase-suspended sectors produces status data on DQ[7:0]. The host can use DQ[7], or DQ[6] and DQ[2] together, to determine if a sector is actively erasing or is erasesuspended. See the Write Operation Status section for information on these status bits. After an erase-suspended program operation is complete, the host can initiate another programming operation (or read operation) within non-suspended sectors. The host can determine the status of a program operation during the Erase-Suspended state just as in the standard programming operation. The host may also write the Electronic ID or CFI Query command sequences when the device is in the Erase Suspend mode. The device allows reading Electronic ID and CFI codes even at addresses within erasing sectors, since the codes are not stored in the memory array. When the Rev. 1.2/May 01 device exits the Electronic ID mode or the CFI Query mode, the device reverts to the Erase Suspend mode, and is ready for another valid operation. See Electronic ID and CFI Query Mode sections for more information. The system must write the Erase Resume command to exit the Erase Suspend mode and continue the sector erase operation. Further writes of the Resume command are ignored. Another Erase Suspend command can be written after the device has resumed erasing. Electronic ID Command The Electronic ID mode provides manufacturer and device identification and sector protection verification through identifier codes output on DQ[7:0]. This mode is intended primarily for programming equipment to automatically match a device to be programmed with its corresponding programming algorithm. Two methods are provided for accessing the Electronic ID data. The first requires VID on address pin A[9], as described previously in the Device Operations section. The Electronic ID data can also be obtained by the host by invoking the Electronic ID command, as shown in Table 6. This method does not require VID. The Electronic ID command sequence may be issued while the device is in the Read mode or in the Erase Suspend Read mode, that is, except while programming or erasing. The Electronic ID command sequence is initiated by writing two unlock cycles, followed by the Electronic ID command. The device then enters the Electronic ID mode, and the system may read at any address any number of times, without initiating another command sequence. * * A read cycle at address 0xXXX00 retrieves the manufacturer code. A read cycle at address 0xXXX01 in Word mode or 0xXXX02 in Byte mode returns the device code. A read cycle containing a sector address (SA) in A[19:12] and the address 0x02 in A[7:0] in Word mode (or 0x04 in A[6:0, -1] in Byte mode) returns 0x01 if that sector is protected, or 0x00 if it is unprotected. * 17 HY29LV160 The system must write the Reset command to exit the Electronic ID mode and return to reading array data. Query Command and Common Flash Interface (CFI) Mode The HY29LV160 is capable of operating in the Common Flash Interface (CFI) mode. This mode allows the host system to determine the manufacturer of the device, its operating parameters, its configuration and any special command codes that the device may accept. With this knowledge, the system can optimize its use of the chip by using appropriate timeout values, optimal voltages and commands necessary to use the chip to its full advantage. Two commands are employed in association with CFI mode. The first places the device in CFI mode (Query command) and the second takes it out of CFI mode (Reset command). These are described in Table 6. Table 7. CFI Mode: Identification Data Values Word Mode Description Query-unique ASCII string "QRY " Primary vendor command set and control interface ID code Address for primary algorithm extended query table Alternate vendor command set and control interface ID code (none) Address for secondary algorithm extended query table (none) Address 10 11 12 13 14 15 16 17 18 19 1A Data 0051 0052 0059 0002 0000 0040 0000 0000 0000 0000 0000 Byte Mode Address 20 22 24 26 28 2A 2C 2E 30 32 34 Data 51 52 59 02 00 40 00 00 00 00 00 The single cycle Query command is valid only when the device is in the Read mode, including during Erase Suspend and Standby states and while in Electronic ID mode, but is ignored otherwise. Read cycles at appropriate addresses while in the Query mode provide CFI data as described later in this section. Write cycles are ignored, except for the Reset command. The Reset command returns the device from the CFI mode to the array Read mode, or to the Erase Suspend mode if the device was in that mode prior to entering CFI mode, or to the Electronic ID mode if the device was in that mode prior to entering CFI mode. The command is valid only when the device is in the CFI mode and as otherwise described for the normal Reset command. Tables 7 - 10 specify the data provided by the HY29LV160 during CFI mode. Data at unspecified addresses reads out as 0x00. Note that a value of 0x00 for a data item normally indicates that the function is not supported. All values in these tables are in hexadecimal. 18 Rev. 1.2/May 01 HY29LV160 Table 8. CFI Mode: System Interface Data Values Word Mode Description VCC supply, minimum (2.7V) VCC supply, maximum (3.6V) VPP supply, minimum (none) VPP supply, maximum (none) Typical timeout for single word/byte write (2N s) Typical timeout for maximum size buffer write (2 s) Typical timeout for individual block erase (2 ms) Typical timeout for full chip erase (2 ms) Maximum timeout for single word/byte write (2 x Typ) Maximum timeout for maximum size buffer write (2N x Typ) Maximum timeout for individual block erase (2N x Typ) Maximum timeout for full chip erase (not supported) N N N N Byte Mode Address 36 38 3A 3C 3E 40 42 44 46 48 4A 4C Data 27 36 00 00 04 00 0A 0F 05 00 03 00 Address 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 Data 0027 0036 0000 0000 0004 0000 000A 000F 0005 0000 0004 0000 Table 9. CFI Mode: Device Geometry Data Values Word Mode Description Device size (2 bytes) Flash device interface code (02 = asynchronous x8/x16) Maximum number of bytes in multi-byte write (not supported) Number of erase block regions Erase block region 1 information [2E, 2D] = # of blocks in region - 1 [30, 2F] = size in multiples of 256-bytes N Byte Mode Address 4E 50 52 54 56 58 5A 5C 5E 60 62 64 66 68 6A 6C 6E 70 72 74 76 78 Data 15 02 00 00 00 04 00 00 40 00 01 00 20 00 00 00 80 00 1E 00 00 01 Address 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C Data 0015 0002 0000 0000 0000 0004 0000 0000 0040 0000 0001 0000 0020 0000 0000 0000 0080 0000 001E 0000 0000 0001 Erase block region 2 information Erase block region 3 information Erase block region 4 information Rev. 1.2/May 01 19 HY29LV160 Table 10. CFI Mode: Vendor-Specific Extended Query Data Values Word Mode Description Query-unique ASCII string "PRI" Major version number, ASCII Minor version number, ASCII Address sensitive unlock (0 = required, 1 = not required) Erase suspend (2 = to read and write) Sector protect (N = # of sectors/group) Temporary sector unprotect (1 = supported) Sector protect/unprotect scheme (4 = Am29LV800A method) Simultaneous R/W operation (0 = not supported) Burst mode type (0 = not supported) Page mode type (0 = not supported) Top/bottom boot version (BB = Bottom Boot, TB = Top Boot) Address 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D Data 0050 0052 0049 0031 0030 0000 0002 0001 0001 0004 0000 0000 0000 0002 (BB) 0003 (TB) Byte Mode Address 80 82 84 86 88 8A 8C 8E 90 92 94 96 98 9A Data 50 52 49 31 30 00 02 01 01 04 00 00 00 02 (BB) 03 (TB) WRITE OPERATION STATUS The HY29LV160 provides a number of facilities to determine the status of a program or erase operation. These are the RY/BY# (Ready/Busy#) pin and certain bits of a status word which can be read from the device during the programming and erase operations. Table 11 summarizes the status indications and further detail is provided in the subsections which follow. RY/BY# - Ready/Busy# RY/BY# is an open-drain output pin that indicates whether a programming or erase Automatic Algorithm is in progress or has completed. A pull-up resistor to VCC is required for proper operation. RY/ BY# is valid after the rising edge of the final WE# pulse in the corresponding command sequence. If the output is Low (busy), the device is actively erasing or programming, including programming while in the Erase Suspend mode. If the output is High (ready), the device has completed the operation and is ready to read array data in the normal or Erase Suspend modes, or it is in the Standby mode. DQ[7] - Data# Polling The Data# ("Data Bar") Polling bit, DQ[7], indicates to the host system whether an Automatic Algorithm is in progress or completed, or whether the 20 device is in Erase Suspend mode. Data# Polling is valid after the rising edge of the final WE# pulse in the Program or Erase command sequence. The system must do a read at the program address to obtain valid programming status information on this bit. While a programming operation is in progress, the device outputs the complement of the value programmed to DQ[7]. When the programming operation is complete, the device outputs the value programmed to DQ[7]. If a program operation is attempted within a protected sector, Data# Polling on DQ[7] is active for approximately 1 s, then the device returns to reading array data. The host must read at an address within any nonprotected sector specified for erasure to obtain valid erase status information on DQ[7]. During an erase operation, Data# Polling produces a "0" on DQ[7]. When the erase operation is complete, or if the device enters the Erase Suspend mode, Data# Polling produces a "1" on DQ[7]. If all sectors selected for erasing are protected, Data# Polling on DQ[7] is active for approximately 100 s, then the device returns to reading array data. If at least one selected sector is not protected, the erase operation erases the unprotected sectors, and ignores the command for the specified sectors that are protected. Rev. 1.2/May 01 HY29LV160 Table 11. Write and Erase Operation Status Summary Mode Operation Programming in progress Normal Programming completed Erase in progress Erase completed 5 DQ[7] Data 0 Data 1 Data 1 DQ[6] Toggle Data Data 4 DQ[5] 0/1 0/1 2 DQ[3] N/A Data 1 3 DQ[2] N/A Data 1 RY/BY# 0 1 0 1 1 1 0 1 DQ[7]# Data 2 Toggle 4 Toggle Data 4 Data 0 Data 0/1 2 Data Data N/A Data N/A Data Read within erase suspended sector Read within non-erase Erase Suspend suspended sector Programming in progress 6 Programming completed 6 No toggle Data Toggle Data 4 Toggle Data N/A Data DQ[7]# Data Notes: 1. A valid address is required when reading status information. See text for additional information. 2. DQ[5] status switches to a `1' when a program or erase operation exceeds the maximum timing limit. 3. A `1' during sector erase indicates that the 50 s time-out has expired and active erasure is in progress. DQ[3] is not applicable to the chip erase operation. 4. Equivalent to `No Toggle' because data is obtained in this state. 5. Data (DQ[7:0]) = 0xFF immediately after erasure. 6. Programming can be done only in a non-suspended sector (a sector not specified for erasure). When the system detects that DQ[7] has changed from the complement to true data (or "0" to "1" for erase), it should do an additional read cycle to read valid data from DQ[7:0]. This is because DQ[7] may change asynchronously with respect to the other data bits while Output Enable (OE#) is asserted low. Figure 7 illustrates the Data# Polling test algorithm. DQ[6] - Toggle Bit I Toggle Bit I on DQ[6] indicates whether an Automatic Program or Erase algorithm is in progress or complete, or whether the device has entered the Erase Suspend mode. Toggle Bit I may be read at any address, and is valid after the rising edge of the final WE# pulse in the Program or Erase command sequence, including during the sector erase time-out. The system may use either OE# or CE# to control the read cycles. Successive read cycles at any address during an Automatic Program algorithm operation (including programming while in Erase Suspend mode) cause DQ[6] to toggle. DQ[6] stops toggling when the operation is complete. If a program address falls within a protected sector, DQ[6] toggles for approximately 1 s after the program command sequence is written, then returns to reading array data. Rev. 1.2/May 01 NO START Read DQ[7:0] at Valid Address (Note 1) Test for DQ[7] = 1? for Erase Operation DQ[7] = Data? YES NO DQ[5] = 1? YES Read DQ[7:0] at Valid Address (Note 1) Test for DQ[7] = 1? for Erase Operation DQ[7] = Data? (Note 2) YES NO PROGRAM/ERASE EXCEEDED TIME ERROR PROGRAM/ERASE COMPLETE Notes: 1. During programming , the program address. During sector erase , an address within any non-protected sector specified for erasure. During chip erase , an address within any non-protected sector. 2. Recheck DQ[7] since it may change asynchronously to DQ[5]. Figure 7. Data# Polling Test Algorithm 21 HY29LV160 START DQ[5] = 1? Read DQ[7:0] at Valid Address (Note 1) NO YES Read DQ[7:0] at Valid Address (Note 1) Read DQ[7:0] at Valid Address (Note 1) Read DQ[7:0] Read DQ[7:0] YES NO (Note 4) DQ[6] Toggled? NO DQ[6] Toggled? (Note 2) NO DQ[2] Toggled? NO (Note 3) PROGRAM/ERASE COMPLETE YES PROGRAM/ERASE EXCEEDED TIME ERROR YES SECTOR BEING READ IS IN ERASE SUSPEND SECTOR BEING READ IS NOT IN ERASE SUSPEND Notes: 1. During programming, the program address. During sector erase, an address within any sector scheduled for erasure. 2. Recheck DQ[6] since toggling may stop at the same time as DQ[5] changes from 0 to 1. 3. Use this path if testing for Program/Erase status. 4. Use this path to test whether sector is in Erase Suspend mode. Figure 8. Toggle Bit I and II Test Algorithm While the Automatic Erase algorithm is operating, DQ[2] toggles when the host reads at addresses successive read cycles at any address cause within sectors that have been specified for eraDQ[6] to toggle. DQ[6] stops toggling when the sure, but cannot distinguish whether the sector is erase operation is complete or when the device is actively erasing or is erase-suspended. DQ[6], placed in the Erase Suspend mode. The host may by comparison, indicates whether the device is acuse DQ[2] to determine which sectors are erasing tively erasing or is in Erase Suspend, but cannot or erase-suspended (see below). After an Erase distinguish which sectors are specified for erasure. command sequence is written, if all sectors seThus, both status bits are required for sector and lected for erasing are protected, DQ[6] toggles for mode information. approximately 100 s, then returns to reading arFigure 8 illustrates the operation of Toggle Bits I ray data. If at least one selected sector is not and II. protected, the Automatic Erase algorithm erases the unprotected sectors, and ignores the selected DQ[5] - Exceeded Timing Limits sectors that are protected. DQ[5] is set to a `1' when the program or erase DQ[2] - Toggle Bit II time has exceeded a specified internal pulse count limit. This is a failure condition that indicates that Toggle Bit II, DQ[2], when used with DQ[6], indithe program or erase cycle was not successfully cates whether a particular sector is actively erascompleted. DQ[5] status is valid only while DQ[7] ing or whether that sector is erase-suspended. or DQ[6] indicate that the Automatic Algorithm is Toggle Bit II is valid after the rising edge of the in progress. final WE# pulse in the command sequence. The device toggles DQ[2] with each OE# or CE# read The DQ[5] failure condition will also be signaled if cycle. the host tries to program a `1' to a location that is previously programmed to `0', since only an erase operation can change a `0' to a `1'. 22 Rev. 1.2/May 01 HY29LV160 For both of these conditions, the host must issue a Reset command to return the device to the Read mode. DQ[3] - Sector Erase Timer After writing a Sector Erase command sequence, the host may read DQ[3] to determine whether or not an erase operation has begun. When the sector erase time-out expires and the sector erase operation commences, DQ[3] switches from a `0' to a `1'. Refer to the "Sector Erase Command" section for additional information. Note that the sector erase timer does not apply to the Chip Erase command. HARDWARE DATA PROTECTION The HY29LV160 provides several methods of protection to prevent accidental erasure or programming which might otherwise be caused by spurious system level signals during VCC power-up and power-down transitions, or from system noise. These methods are described in the sections that follow. Command Sequences Commands that may alter array data require a sequence of cycles as described in Table 6. This provides data protection against inadvertent writes. Low VCC Write Inhibit To protect data during VCC power-up and powerdown, the device does not accept write cycles when VCC is less than VLKO (typically 2.4 volts). The command register and all internal program/erase circuits are disabled, and the device resets to the Read mode. Writes are ignored until VCC is greater than VLKO. The system must provide the proper signals to the control pins to prevent unintentional writes when VCC is greater than VLKO. Write Pulse "Glitch" Protection Noise pulses of less than 5 ns (typical) on OE#, CE# or WE# do not initiate a write cycle. Logical Inhibit Write cycles are inhibited by asserting any one of the following conditions: OE# = VIL , CE# = VIH, or WE# = VIH. To initiate a write cycle, CE# and WE# must be a logical zero while OE# is a logical one. Power-Up Write Inhibit If WE# = CE# = VIL and OE# = VIH during power up, the device does not accept commands on the rising edge of WE#. The internal state machine is automatically reset to the Read mode on powerup. Sector Protection Additional data protection is provided by the HY29LV160's sector protect feature, described previously, which can be used to protect sensitive areas of the Flash array from accidental or unauthorized attempts to alter the data. After the initial Sector Erase command sequence is issued, the system should read the status on DQ[7] (Data# Polling) or DQ[6] (Toggle Bit I) to ensure that the device has accepted the command sequence, and then read DQ[3]. If DQ[3] is a `1', the internally controlled erase cycle has begun and all further sector erase data cycles or commands (other than Erase Suspend) are ignored until the erase operation is complete. If DQ[3] is a `0', the device will accept a sector erase data cycle to mark an additional sector for erasure. To ensure that the data cycles have been accepted, the system software should check the status of DQ[3] prior to and following each subsequent sector erase data cycle. If DQ[3] is high on the second status check, the last data cycle might not have been accepted. Rev. 1.2/May 01 23 HY29LV160 ABSOLUTE MAXIMUM RATINGS 4 Symbol TSTG TBIAS VIN2 I OS Storage Temperature Ambient Temperature with Power Applied Voltage on Pin with Respect to VSS : VCC 1 A[9], OE#, RESET# 2 All Other Pins 1 Output Short Circuit Current 3 Parameter Value -65 to +150 -55 to +125 -0.5 to +4.0 -0.5 to +12.5 -0.5 to VCC +0.5 200 Unit C C V V V mA Notes: 1. Minimum DC voltage on input or I/O pins is -0.5 V. During voltage transitions, input or I/O pins may undershoot VSS to -2.0V for periods of up to 20 ns. See Figure 9. Maximum DC voltage on input or I/O pins is VCC + 0.5 V. During voltage transitions, input or I/O pins may overshoot to VCC +2.0 V for periods up to 20 ns. See Figure 10. 2. Minimum DC input voltage on pins A[9], OE#, and RESET# is -0.5 V. During voltage transitions, A[9], OE#, and RESET# may undershoot VSS to -2.0 V for periods of up to 20 ns. See Figure 9. Maximum DC input voltage on pin A[9] is +12.5 V which may overshoot to 14.0 V for periods up to 20 ns. 3. No more than one output at a time may be shorted to VSS. Duration of the short circuit should be less than one second. 4. Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational sections of this data sheet is not implied. Exposure of the device to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS 1 Symbol TA Parameter Ambient Operating Temperature: Commercial Temperature Devices Industrial Temperature Devices Operating Supply Voltage: -70, -90V and -12V Versions All Other Versions Value 0 to +70 -40 to +85 +3.0 to +3.6 +2.7 to +3.6 Unit C C V V V CC Notes: 1. Recommended Operating Conditions define those limits between which the functionality of the device is guaranteed. 20 ns 0.8 V - 0.5 V 20 ns V C C + 2.0 V 20 ns V C C + 0.5 V - 2.0 V 20 ns 2.0 V 20 ns 20 ns Figure 9. Maximum Undershoot Waveform Figure 10. Maximum Overshoot Waveform 24 Rev. 1.2/May 01 HY29LV160 DC CHARACTERISTICS Parameter Description Input Load Current ILI ILIT A[9] Input Load Current ILO Output Leakage Current Test Setup 2 VIN = VSS to VCC A[9] = 12.5 V VOUT = VSS to VCC CE# = VIL, 5 MHz OE# = VIH, 1 MHz Byte Mode CE# = VIL, 5 MHz OE# = VIH, 1 MHz Word Mode CE# = VIL, OE# = VIH CE# = VCC 0.3 V, RESET# = VCC 0.3 V RESET# = VSS 0.3 V VIH = VCC 0.3 V, VIL = VSS 0.3 V CE# = RESET# = VIH RESET# = VIL -0.5 0.7 x VCC VCC = 3.3V VCC = VCC Min, IOL = 4.0 mA VCC = VCC Min, IOH = -2.0 mA VCC = VCC Min, IOH = -100 A 11.5 Min Typ Max 1.0 35 1.0 16 4 16 4 50 5 5 5 1 1 0.8 VCC + 0.3 12.5 0.45 0.85 x VCC VCC - 0.4 2.3 2.5 Unit A A A mA mA mA mA mA A A A mA mA V V V V V V V 9 2 9 2 30 1 1 1 ICC1 VCC Active Read Current 1 ICC2 ICC3 ICC4 ICC5 ICC6 ICC7 VIL VIH VID VOL VOH1 VCC Active Write Current VCC CE# Controlled Deep Standby Current VCC RESET# Controlled Deep Standby Current Automatic Sleep Mode Current 5, VCC CE# Controlled Normal Standby Current 2 VCC RESET# Controlled Normal Standby Current 2 Input Low Voltage Input High Voltage Voltage for Electronic ID and Temporary Sector Unprotect Output Low Voltage 3, 4 Output High Voltage VOH2 VLKO Low VCC Lockout Voltage4 Notes: 1. The ICC current is listed is typically less than 2 mA/MHz with OE# at VIH. Typical VCC is 3.0 V. 2. All specifications are tested with VCC = VCC Max unless otherwise noted. 3. ICC active while the Automatic Erase or Automatic Program algorithm is in progress. 4. Not 100% tested. 5. Automatic sleep mode is enabled when addresses remain stable for tACC + 30 ns (typical). Rev. 1.2/May 01 25 HY29LV160 DC CHARACTERISTICS Zero Power Flash 20 15 Supply Current in mA 10 5 0 0 500 1000 1500 2000 Time in ns Note: Addresses are switching at 1 MHz. 2500 3000 3500 4000 Figure 11. ICC1 Current vs. Time (Showing Active and Automatic Sleep Currents) 10 3.6 V 8 Supply Current in mA 2.7 V 6 4 2 0 1 Note: T = 25 C. 2 3 Frequency in MHz 4 5 6 Figure 12. Typical ICC1 Current vs. Frequency 26 Rev. 1.2/May 01 HY29LV160 KEY TO SWITCHING WAVEFORMS WAVEFORM INPUT S Steady OUT PUT S Changing from H to L Changing from L to H Don't Care, Any Change Permitted Changing, State Unknown Centerline is High Impedance State (High Z) Does Not Apply TEST CONDITIONS Table 12. Test Specifications + 3.3V Test Condition 2.7 KOhm - 70 - 80 30 5 0.0 3.0 1.5 1.5 - 90 - 12 100 Unit Output Load Output Load Capacitance (CL) Input Rise and Fall Times Input Signal Low Level Input Signal High Level Low Timing Measurement Signal Level High Timing Measurement Signal Level 1 TTL Gate pF ns V V V V DEVICE UNDER TEST CL 6.2 KOhm All diodes are 1N3064 or equivalent Figure 13. Test Setup Note: Timing measurements are made at the reference levels specified above regardless of where the illustrations in the timing diagrams appear to indicate the measurement is made 3.0 V Input 0.0 V 1.5 V Measurement Level 1.5 V Output Figure 14. Input Waveforms and Measurement Levels Rev. 1.2/May 01 27 HY29LV160 AC CHARACTERISTICS Read Operations Parameter JEDEC tAVAV tAVQV tELQV tEHQZ tGLQV tGHQZ Std tRC tACC tCE tDF t OE tDF tOEH tAXQX t OH Description Read Cycle Time 1 Address to Output Delay Chip Enable to Output Delay Chip Enable to Output High Z 1 Output Enable to Output Delay Output Enable to Output High Z Output Enable Hold Time 1 Read Toggle and Data# Polling 1 Test Setup Min CE# = VIL OE# = VIL OE# = VIL CE# = VIL Max Max Max Max Max Min Min Min Speed Option - 70 - 80 70 70 70 25 30 25 80 80 80 25 30 25 0 10 0 - 90 90 90 90 30 35 30 - 12 120 120 120 30 50 30 Unit ns ns ns ns ns ns ns ns ns Output Hold Time from Addresses, CE# or OE#, Whichever Occurs First 1 Notes: 1. Not 100% tested. 2. See Figure 13 and Table 12 for test conditions. tR C Addresses Addresses Stable tA C C CE# tO E OE# tO E H WE# tC E tD F tO H Output Valid Outputs RESET# RY/BY# 0V Figure 15. Read Operation Timings 28 Rev. 1.2/May 01 HY29LV160 AC CHARACTERISTICS Hardware Reset (RESET#) Parameter JEDEC Std tREADY tREADY tRP tRH tRPD tRB Description RESET# Pin Low (During Automatic Algorithms) to Read or Write 1 RESET# Pin Low (NOT During Automatic Algorithms) to Read or Write 1 RESET# Pulse Width RESET# High Time Before Read 1 RESET# Low to Standby Mode RY /BY # Recovery Time Test Setup Max Max Min Min Max Min Speed Option - 70 - 80 - 90 20 500 500 50 20 0 - 12 Unit s ns ns ns s ns Notes: 1. Not 100% tested. 2. See Figure 13 and Table 12 for test conditions. RY/BY# CE#, OE# 0V tR H RESET# tR P t Ready Reset Timings NOT During Automatic Algorithms RY/BY# CE#, OE# RESET# tR P t Ready tRB Reset Timings During Automatic Algorithms Figure 16. RESET# Timings Rev. 1.2/May 01 29 HY29LV160 AC CHARACTERISTICS Word/Byte Configuration (BYTE#) Parameter JEDEC Std tELFL tELFH tFLQZ tFHQV Description CE# to BY TE# Switching Low CE# to BY TE# Switching High BY TE# Switching Low to Output High-Z BY TE# Switching High to Output Active Max Max Max Min 25 70 25 80 Speed Option - 70 - 80 5 5 30 90 30 120 - 90 - 12 Unit ns ns ns ns CE# OE# BYTE# BYTE# switching from word to byte mode DQ[14:0] DQ[15]/A-1 tF L Q Z BYTE# DQ[14:0] Data Output DQ[7:0] Data Output DQ[14:0] tELFL Data Output DQ[14:0] Data Output DQ[7:0] Output DQ[15] Address Input A-1 BYTE# switching from byte to word mode DQ[15]/A-1 tE L F H Address Input A-1 Data Output DQ[15] tF H Q V Figure 17. BYTE# Timings for Read Operations CE# Falling edge of the last WE# signal WE# t S E T (t A S ) BYTE# Note: Refer to the Program/Erase Operations table for tAS and tAH specifications. t H O L D (t A H ) Figure 18. BYTE# Timings for Write Operations 30 Rev. 1.2/May 01 HY29LV160 AC CHARACTERISTICS Program and Erase Operations Parameter JEDEC tAVAV tAVWL tWLAX tDVWH tWHDX tGHWL tELWL tWHEH tWLWH tWHWL Std t WC tAS tAH tDS tDH tCS tCH t WP tWPH Write Cycle Time 1 Address Setup Time Address Hold Time Data Setup Time Data Hold Time CE# Setup Time CE# Hold Time Write Pulse Width Write Pulse Width High Byte Mode tWHWH1 tWHWH1 Programming Operation 1, 2, 3 Word Mode Byte Mode Chip Programming Operation 1, 2, 3, 5 Word Mode tWHWH2 tWHWH3 tWHWH2 Sector Erase Operation 1, 2, 4 tWHWH3 Chip Erase Operation 1, 2, 4 Description Min Min Min Min Min Min Min Min Min Min Typ Max Typ Max Typ Max Typ Max Typ Max Typ Typ Min Min Min Min Speed Option - 70 - 80 70 45 35 80 0 45 35 0 0 0 0 35 35 30 9 300 18 500 18 54 18 54 0.25 5 8 1,000,000 100,000 50 0 90 35 50 45 45 50 50 - 90 90 - 12 120 Unit ns ns ns ns ns ns ns ns ns ns s s s s sec sec sec sec sec sec sec cycles cycles s ns ns tGHWL Read Recovery Time Before Write Erase and Program Cycle Endurance 1 tVCS tRB tBUSY VCC Setup Time 1 Recovery Time from RY /BY # WE# High to RY /BY # Delay Notes: 1. Not 100% tested. 2. Typical program and erase times assume the following conditions: 25 C, VCC = 3.0 volts, 100,000 cycles. In addition, programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 C, VCC = 2.7 volts (3.0 volts for - 70 version), 100,000 cycles. 3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. See Table 6 for further information on command sequences. 4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes are programmed to 0x00 before erasure. 5. The typical chip programming time is considerably less than the maximum chip programming time listed since most bytes/words program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum byte/word program time specified is exceeded. See Write Operation Status section for additional information. Rev. 1.2/May 01 31 HY29LV160 AC CHARACTERISTICS Program Command Sequence (last two cycles) Read Status Data (last two cycles) tW C Addresses CE# tG H W L OE# WE# tC S tD S 0xA0 tW P 0x555 tA S PA tA H PA PA tC H tW P H tD H tW H W H 1 PD tB U S Y Status D OUT tR B Data RY/BY# V CC tV C S Notes: 1. PA = Program Address, PD = Program Data, DOUT is the true data at the program address. 2. Commands shown are for Word mode operation. 3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence. Figure 19. Program Operation Timings 32 Rev. 1.2/May 01 HY29LV160 AC CHARACTERISTICS Erase Command Sequence (last two cycles) Read Status Data (last two cycles) tW C Addresses CE# tG H W L OE# tW P WE# tC S tD S tC H 0x2AA tA S SA tA H VA Address = 0x555 for chip erase VA tW P H tD H Data = 0x10 for chip erase t W H W H 2 or tW H W H 3 Status D OUT tR B Data 0x55 0x30 tB U S Y RY/BY# V CC tV C S Notes: 1. SA =Sector Address (for sector erase), VA = Valid Address for reading status data (see Write Operation Status section), DOUT is the true data at the read address.(0xFF after an erase operation). 2. Commands shown are for Word mode operation. 3. VCC shown only to illustrate tVCS measurement references. It cannot occur as shown during a valid command sequence. Figure 20. Sector/Chip Erase Operation Timings Rev. 1.2/May 01 33 HY29LV160 AC CHARACTERISTICS tR C Addresses tC H CE# tC E OE# tO E H WE# tO E tD F tO H Complement Complement True Valid Data VA tA C C VA VA DQ[7] DQ[6:0] tB U S Y RY/BY# Status Data Status Data Data Valid Data Notes: 1. VA = Valid Address for reading Data# Polling status data (see Write Operation Status section). 2. Illustration shows first status cycle after command sequence, last status read cycle and array data read cycle. Figure 21. Data# Polling Timings (During Automatic Algorithms) tR C Addresses tC H CE# tC E OE# tO E H WE# tO E tD F tO H Valid Status Valid Status (second read) Valid Status (stops toggling) Valid Data VA tA C C VA VA VA DQ[6], [2] tB U S Y RY/BY# (first read) Notes: 1. VA = Valid Address for reading Toggle Bits (DQ[2], DQ[6]) status data (see Write Operation Status section). 2. Illustration shows first two status read cycles after command sequence, last status read cycle and array data read cycle. Figure 22. Toggle Polling Timings (During Automatic Algorithms) 34 Rev. 1.2/May 01 HY29LV160 AC CHARACTERISTICS Enter Automatic Erase Erase Suspend Erase Erase Suspend Read Enter Erase Suspend Program Erase Suspend Program Erase Resume Erase Suspend Read Erase Erase Complete WE# DQ[6] DQ[2] Notes: 1. The system may use CE# or OE# to toggle DQ[2] and DQ[6]. DQ[2] toggles only when read at an address within an erase-suspended sector. Figure 23. DQ[2] and DQ[6] Operation In-System Sector Protect and Unprotect, Temporary Sector Unprotect Parameter JEDEC Std tVIDR tRSP tVRST tPROT tUNPR Description VID Transition Time for Temporary Sector Unprotect 1 RESET# Setup Time for Temporary Sector Unprotect RESET# Setup Time for In-System Sector Protect and Unprotect In-System Sector Protect Time In-System Sector Unprotect Time Min Min Min Max Max Speed Option - 70 - 80 - 90 - 12 500 4 1 150 15 Unit ns s s s ms Notes: 1. Not 100% tested. V ID RESET# 0 or 3V 0 or 3V t VIDR t VIDR CE# WE# tR S P RY/BY# Figure 24. Temporary Sector Unprotect Timings Rev. 1.2/May 01 35 HY29LV160 AC CHARACTERISTICS V ID RESET# V IH SA, A[6], A[1], A[0] Data tV R E S Don't Care Valid * Valid * Verify 0x40 tP R O T Valid * Sector Protect/Unprotect 0x60 0x60 Status CE# tU N P R WE# OE# Note: For Sector Protect, A[6] = 0, A[1] = 1, A[0] = 0. For Sector Unprotect, A[6] = 1, A[1] = 1, A[0] = 0. Figure 25. In-System Sector Protect and Unprotect Timings 36 Rev. 1.2/May 01 HY29LV160 AC CHARACTERISTICS Alternate CE# Controlled Erase/Program Operations Parameter JEDEC tAVAV tAVEL tELAX tDVEH tEHDX tGHEL tWLEL tEHWH tELEH tEHEL Std t WC tAS tAH tDS tDH t WS t WH tCP tCPH Write Cycle Time 1 Address Setup Time Address Hold Time Data Setup Time Data Hold Time WE# Setup Time WE# Hold Time CE# Pulse Width CE# Pulse Width High Byte Mode tWHWH1 tWHWH1 Programming Operation 1, 2, 3 Word Mode Byte Mode Chip Programming Operation 1, 2, 3, 5 Word Mode Description Min Min Min Min Min Min Min Min Min Min Typ Max Typ Max Typ Max Typ Max Typ Max Typ Typ Min Min 35 35 30 9 300 18 500 18 54 18 54 0.25 5 8 1,000,000 100,000 90 45 35 45 35 0 0 0 0 35 50 Speed Option - 70 - 80 70 80 0 45 45 50 50 - 90 90 - 12 120 Unit ns ns ns ns ns ns ns ns ns ns s s s s sec sec sec sec sec sec sec cycles cycles ns tGHEL Read Recovery Time Before Write tWHWH2 tWHWH3 tWHWH2 Sector Erase Operation 1, 2, 4 tWHWH3 Chip Erase Operation 1, 2, 4 Erase and Program Cycle Endurance 1 tBUSY CE# to RY /BY # Delay Notes: 1. Not 100% tested. 2. Typical program and erase times assume the following conditions: 25 C, VCC = 3.0 volts, 100,000 cycles. In addition, programming typicals assume a checkerboard pattern. Maximum program and erase times are under worst case conditions of 90 C, VCC = 2.7 volts (3.0 volts for 70 ns version), 100,000 cycles. 3. Excludes system-level overhead, which is the time required to execute the four-bus-cycle sequence for the program command. See Table 6 for further information on command sequences. 4. Excludes 0x00 programming prior to erasure. In the preprogramming step of the Automatic Erase algorithm, all bytes are programmed to 0x00 before erasure. 5. The typical chip programming time is considerably less than the maximum chip programming time listed since most bytes program faster than the maximum programming times specified. The device sets DQ[5] = 1 only If the maximum byte program time specified is exceeded. See Write Operation Status section for additional information. Rev. 1.2/May 01 37 HY29LV160 AC CHARACTERISTICS PA for Program SA for Sector Erase 0x555 for Chip Erase 0x555 for Program 0x2AA for Erase Addresses tW C WE# tG H E L OE# tW S CE# tD S Data 0xA0 for Program 0x55 for Erase PD for Program 0x30 for Sector Erase 0x10 for Chip Erase VA tA S tA H tW H tC P tC P H t W H W H 1 or t W H W H 2 or t W H W H 3 tB U S Y Status D OUT tD H RY/BY# tR H RESET# Notes: 1. PA = program address, PD = program data, VA = Valid Address for reading program or erase status (see Write Operation Status section), DOUT = array data read at VA. 2. 3. 4. Illustration shows the last two cycles of the program or erase command sequence and the last status read cycle. Word mode addressing shown. RESET# shown only to illustrate tRH measurement references. It cannot occur as shown during a valid command sequence. Figure 26. Alternate CE# Controlled Write Operation Timings 38 Rev. 1.2/May 01 HY29LV160 Latchup Characteristics Description Input voltage with respect to VSS on all pins except I/O pins(including A[9], OE# and RESET#) Input voltage with respect to VSS on all I/O pins VCC Current Minimum - 1.0 - 1.0 - 100 Maximum 12.5 VCC + 1.0 100 Unit V V mA Notes: 1. Includes all pins except VCC. Test conditions: VCC = 3.0V, one pin at a time. TSOP Pin Capacitance Symbol CIN COUT CIN2 Parameter Input Capacitance Output Capacitance Control Pin Capacitance Test Setup VIN = 0 VOUT = 0 VIN = 0 Typ 6 8.5 7.5 Max 7.5 12 9 Unit pF pF pF Notes: 1. Sampled, not 100% tested. 2. Test conditions: TA = 25 C, f = 1.0 MHz. Data Retention Parameter Minimum Pattern Data Retention Time Test Conditions 150 C 125 C Minimum 10 20 Unit Years Years Rev. 1.2/May 01 39 HY29LV160 PACKAGE DRAWINGS Physical Dimensions TSOP48 - 48-pin Thin Small Outline Package (measurements in millimeters) 0.95 1.05 Pin 1 ID 1 48 11.90 12.10 0.50 BSC 24 25 18.30 18.50 19.80 20.20 0.05 0.15 1.20 MAX 0.25MM (0.0098") BSC 0 o 5 0.50 0.70 o 0.08 0.20 0.10 0.21 40 Rev. 1.2/May 01 HY29LV160 PACKAGE DRAWINGS Physical Dimensions FBGA48 - 48-Ball Fine-Pitch Ball Grid Array, 8 x 9 mm (measurements in millimeters) Note: Unless otherwise specified, tolerance = 0.05 0.10 C 9.00 0.10 A 1.80 0.10 A1 CORNER INDEX AREA 2.10 0.10 C 8.00 0.10 0.10 C B C 1.10 MAX 0.20 MIN 5.60 BSC 0.76 TYP 0.10 C Seating Plane C 0.08 C H G F E D C B A 6 5 4 0.40 BSC 4.00 BSC 3 2 1 0.80 TYP C O 0.30 0.05 O 0.15 M C A B O 0.08 M C 0.40 BSC Pin A1 Index Mark C Rev. 1.2/May 01 41 HY29LV160 APPENDIX SECTOR PROTECTION/UNPROTECTION USING PROGRAMMING EQUIPMENT In addition to in-situ sector protection/unprotection, described in the Bus Operations section, the HY29LV160 is capable of performing the same functions using programming equipment. This appendix describes the procedures and provides specifications for these functions. Sector Protect The hardware sector protection feature disables both program and erase operations in any sector or combination of sectors. The method intended for programming equipment requires a high voltage (VID) on address pin A[9] and the OE# pin. The flow chart in Figure A1 illustrates the algorithm, and timing specifications and waveforms are provided at the end of this section. When implementing the algorithm, note that VCC must be applied to the device before applying VID, and VID should be removed before removing VCC from the device. Programming of the protection circuitry begins on the falling edge of WE# and is terminated on the rising edge of the same pulse. Verification of protection is done as described in the Electronic ID Mode section and shown in the flow chart. The HY29LV160 is shipped with all sectors unprotected. Sector Unprotect The hardware sector unprotection feature re-enables both program and erase operations in previously protected sectors. Note that to unprotect any sector, all unprotected sectors must first be protected prior to the first sector unprotect write cycle. The method intended for programming equipment requires a high voltage (VID) on address pin A[9] and the OE# pin. The flow chart in Figure A2 illustrates the algorithm, and timing specifications and waveforms are given at the end of this section. When implementing the algorithm, note that VCC must be applied to the device before applying VID, and VID should be removed before removing VCC from the device. DC CHARACTERISTICS Sector Protection and Unprotection Using Programming Equipment Parameter VCC VID ILIT VIL VIH Description Operating Power Supply Voltage for Sector Protect, Unprotect VCC = 3.0 V and Verify High Voltage Input Load Current (A[9], OE#) Input Low Voltage Input High Voltage VCC = VCC Max A[9] = OE# = 12.5 V -0.5 2.0 Test Conditions Min 3.0 11.5 Max 3.6 12.5 35 0.8 VCC + 0.5 Unit V V A V V Sector Protection and Unprotection Verification Using Programming Equipment 1 Operation Sector Protect Verification L Sector Unprotect Verification Notes: 1. L = VIL, H = VIH. CE# OE# WE# RESET # A[19:12] A[9] A[6] A[1] A[0] L H H Sector VID Address L H H L DQ[7:0] 0x01 0x00 42 Rev. 1.2/May 01 HY29LV160 AC CHARACTERISTICS Sector Protection and Unprotection Using Programming Equipment Parameter JEDEC Std tVIDR tST t OE tWPP1 tWPP2 tOESP tCSP Voltage Setup Time Output Enable to Output Delay Write Pulse Width for Sector Protect Operation Write Pulse Width for Sector Unprotect Operation OE# Setup Time to WE# Active 1 CE# Setup Time to WE# Active 1 Description Voltage Transition Time 1 Min Min Max Min Min Min Min Speed Option - 70 - 80 4 30 30 15 4 4 35 150 50 - 90 - 12 500 Unit ns s ns s ms s s Notes: 1. Not 100% tested. START Wait 150 us APPLY V CC Set TRYCNT = 1 A[9] = V ID A[19:12] = Sector to Protect OE# = CE# = V IL A[6] = A[0] = V IL WE# = RESET# = A[1] = V IH Wait 4 us Increment TRYCNT Remove V ID from A[9] A9 = OE# = V ID Read Data NO Set Address: A[19:12] = Sector to Protect CE# = A[6] = A]0] = V IL RESET# = A[1] = V IH Write Reset Command Data = 0x01? NO TRYCNT = 25? Wait 4 us YES YES WE# = V IL Protect Another Sector? NO SECTOR PROTECT COMPLETE DEVICE FAILURE YES Figure A1. Sector Protection Using Programming Equipment Rev. 1.2/May 01 43 HY29LV160 START NOTE: All sectors must be previously protected. See Figure A1. A P P L Y V CC SET A[9] = V ID OE# = CE# = A[0] = V IL W E # = V IH RESET# = A[1] = A[6] = V IH Wait 4 us Set TRYCNT = 1 SET NSEC = 0 SET Sector Address: A[19:12] = Sector NSEC S E T A [ 9 ] = O E # = V ID Read Data SET CE# = A[0] = V IL RESET# = A[1] = A[6] = V IH Data = 0x00? Wait 4 us YES YES NO NO YES TRYCNT = 1000? Increment TRYCNT W E # = V IL NSEC = 34? Wait 15 ms NO NSEC = NSEC + 1 R e m o v e V ID from A[9] SECTOR UNPROTECT COMPLETE DEVICE FAILURE Figure A2. Sector Unprotect Using Programming Equipment 44 Rev. 1.2/May 01 HY29LV160 AC CHARACTERISTICS A[19:12] A[0] A[1] A[6] V ID SA X SA Y t VIDR tS T t VIDR A[9] V ID OE# t VIDR tO E S P tW P P 1 WE# CE# tC S P Data RESET# V CC tS T tO E 0x01 Figure A3. Timings for Sector Protection Using Programming Equipment Rev. 1.2/May 01 45 HY29LV160 AC CHARACTERISTICS A[19:12] A[0] A[1] A[6] V ID SA 0 SA 1 t VIDR tS T tS T t VIDR A[9] V ID OE# t VIDR tW P P 2 WE# CE# Data RESET# V CC tO E S P tC S P 0x00 tO E Figure A4. Timings for Sector Unprotect Using Programming Equipment 46 Rev. 1.2/May 01 HY29LV160 ORDERING INFORMATION Hynix products are available in several speeds, packages and operating temperature ranges. The ordering part number is formed by combining a number of fields, as indicated below. Refer to the `Valid Combinations' table, which lists the configurations that are planned to be supported in volume. Please contact your local Hynix representative or distributor to confirm current availability of specific configurations and to determine if additional configurations have been released. HY29LV160 X X X X X SPECIAL INSTRUCTIONS TEMPERATURE RANGE Blank = Commercial ( 0 to +70 C) I = Industrial (-40 to +85 C) SPEED OPTION 70 80 90 12 PACKAGE TYPE T = 48-Pin Thin Small Outline Package (TSOP) F = 48-Ball Fine-Pitch Ball Grid Array (FBGA), 8 x 9 mm BOOT BLOCK LOCATION T = Top Boot Block Option B = Bottom Boot Block Option DEVICE NUMBER HY29LV160 = 16 Megabit (2M x 8/1M x 16) CMOS 3 Volt-Only Sector Erase Flash Memory = = = = 70 ns 80 ns 90 ns 120 ns VALID COMBINATIONS P ackag e an d S p eed FBGA Temperature Commercial Industrial Commercial Industrial 70 n s --F-70 F-70I 80 n s F-80 F-80I --90 n s 120 n s 70 n s Operating Voltage = 2.7 - 3.6 Volts F-90 F-12 -T-80 F-90I F-12I -T-80I Operating Voltage = 3.0 - 3.6 Volts ----T-70 T-70I --T-90 T-90I T-90V -T-12 T-12I T-12V -TSOP 80 n s 90 n s 120 n s Note: 1. The complete part number is formed by appending the Boot Block Location code and the suffix shown in the table to the Device Number. For example, the part number for a 90 ns, Industrial temperature range device in the TSOP package with the top boot block option is HY29LV160TT-90I. Rev. 1.2/May 01 47 HY29LV160 Important Notice (c) 2001 by Hynix Semiconductor America. All rights reserved. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Hynix Semiconductor Inc. or Hynix Semiconductor America (collectively "Hynix"). The information in this document is subject to change without notice. Hynix shall not be responsible for any errors that may appear in this document and makes no commitment to update or keep current the information contained in this document. Hynix advises its customers to obtain the latest version of the device specification to verify, before placing orders, that the information being relied upon by the customer is current. Devices sold by Hynix are covered by warranty and patent indemnification provisions appearing in Hynix Terms and Conditions of Sale only. Hynix makes no warranty, express, statutory, implied or by description, regarding the information set forth herein or regarding the freedom of the described devices from intellectual property infringement. Hynix makes no warranty of merchantability or fitness for any purpose. Hynix's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to such intended use is executed between the customer and Hynix prior to use. Life support devices or systems are those which are intended for surgical implantation into the body, or which sustain life whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. Revision Record Rev. 1.2 Date 5/01 Details Change to Hynix format. Corrected description of FBGA view in Pin Configurations section. Removed Extended temperature option. Added -90V and -12V device options. Memory Sales and Marketing Division Hynix Semiconductor Inc. 10 Fl., Hynix Youngdong Building 89, Daechi-dong Kangnam-gu Seoul, Korea Telephone: +82-2-580-5000 Fax: +82-2-3459-3990 http://www.hynix.com 48 Flash Memory Business Unit Hynix Semiconductor America Inc. 3101 North First Street San Jose, CA 95134 USA Telephone: (408) 232-8800 Fax: (408) 232-8805 http://www.us.hynix.com Rev. 1.2/May 01 |
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